Field of the Invention
The invention relates to a method for selective filtering with a coefficient and filter calculation unit, a phase detector, a loop filter, and a digital oscillator, these units simulating different selective filters depending on coefficients used for the filter calculation.
Systems for receiving digital data generally require a device for recovering the data clock signal implicitly contained in the signal. In principle, there are two approaches for receiving the data: (1) the clock control loop contains the circuit that supplies the sampling clock of the analog/digital converter (xe2x80x9cADCxe2x80x9d) (e.g. VCXO); and (2) the clock signal of the ADC is asynchronous with respect to the data clock. A fully digital control circuit calculates by interpolation from the output values of the ADC samples in a timing pattern that is synchronous with the data clock. There exist prior art circuits that achieve the task in baseband. Most applications have filters upstream or downstream of the ADC, which filters select the signal that is intended to be processed, i.e., suppress adjacent signals and other interference signals. These filters are generally optimized for a fixed bandwidth or data rate, such as, e.g., surface acoustic wave filters. Stringent requirements regarding phase linearity are usually imposed on the filter so that the pulse shape of the data signals is not distorted.
Basic theories with regard to fully digital clock recovery in digital modems by interpolation are discussed in an article by Floyd M. Gardener titled xe2x80x9cInterpolation in Digital-Modems -Part I: Fundamentalsxe2x80x9d. The article appeared in the journal IEEE Transactions on Communications, Vol. 41, No. 3, in March 1993.
A further approach in the prior art uses analog filters having a controllable bandwidth upstream of the ADC. However, these filters are expensive and, particularly in CMOS technology, are difficult to integrate on a circuit. Analog filters fundamentally have phase distortions that have to be reduced using additional circuits. Moreover, the sampling frequency of the ADC has to be adapted to the signal bandwidth.
Another approach lies in providing a multistage digital selection filter upstream of the clock recovery and in carrying out the fine adjustment of the sampling frequency by interpolation again. After each stage of the filter, the sampling rate is reduced by a fixed factor. The approach has a disadvantage in that many filter stages are required for small bandwidths. Thus, the filter becomes complicated. Moreover, a fixed gradation means that not all the interference components can be suppressed, which generally leads to an increase in outlay in the downstream interpolator.
Lambrette U et al.: xe2x80x9cVARIABLE SAMPLE RATE DIGITAL FEEDBACK AND TIMING SYNCHRONIZATIONxe2x80x9d in I.E.E.E. Vehicular Technology Conference, New York, USA, I.E.E.E., Bd. Conf. 47, pages 1348-1352, discusses two algorithms for digital receivers for processing a broader range of different sampling rates. One of the algorithms is also based on filtering the received signals prior to the time synchronization. A time synchronization algorithm is presented that is not data-aided, is based on digital feedback, and can process symbol rates deviating from a sampling rate.
The paper by D. Kim et al.: xe2x80x9cDESIGN OF OPTIMAL INTERPOLATION FILTER FOR SYMBOL TIMING RECOVERYxe2x80x9d in I.E.E.E. Transactions on Communications, I.E.E.E. Inc., New York, USA, Vol. 45, No. 7, pages 877-884, discloses an optimized interpolation filter for recovering the symbol timing in a digital receiver, in which the sampling rate of the analog-to-digital converter on the input side is not synchronized with the symbol clock of the transmitter.
The paper by K. Bucket et al. xe2x80x9cPERIODIC TIMING ERROR COMPONENTS IN FEEDBACK SYNCHRONIZERS OPERATING ON NONSYNCHRONIZED SIGNAL SAMPLESxe2x80x9d I.E.E.E. Transactions on Communications, I.E.E.E. Inc., New York, USA, Vol. 46, No. 6, pages 747-749, reveals that the synchronization error contains periodic components through a loop for timing recovery on detection of nonsynchronized samples of a noisy sine signal. These periodic errors are produced exclusively by non-ideal interpolation between the nonsynchronized signal samples and disappear when synchronized sampling is performed.
It is accordingly an object of the invention to provide a method for selective filtering that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that can be realized with little outlay.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a method for selective filtering, including the steps of simulating different selective filters with a coefficient and filter calculation unit, a phase detector, a loop filter, and a digital oscillator depending on first and second coefficients used for filter calculation, determining the first coefficients of a prototype of a further selective filter at a characteristic frequency fc forxe2x80x94given sampling frequency fa, calculating the second coefficients of the further selective filter at a characteristic frequency fc2 from the first coefficients at points tk=xcex94t+k*d, where k=0, 1, . . . , the further selective filter to be operated at a sampling rate fa1, by interpolating values of a continuous-time impulse response of a simulation of the further selective filter at points tk, where       d    =                  fc2        *        fa                    fc        *                  fa          1                      ,
simulating the further selective filter with the second coefficients using the coefficient and filter calculation unit, the phase detector, the loop filter, and the digital oscillator, and operating the further selective filter at the sampling rate fa1.
The approach employed by the invention is to use a filter disclosed in International PCT publication WO-A-00/02311, filed Jan. 13, 2000, corresponding to PCT/DE 99/01878 and U.S. patent application Ser. No. 09/752,923 filed Jan. 2, 2001 by the same inventor and to combine it with a variant of a prior art clock recovery circuit with an interpolation filter. As such, the approach of deriving filter coefficients from the coefficients of a prototype filter is extended in order to additionally realize a variable delay that is required for the interpolation of the data signal and that must generally be shorter than the period of the ADC clock signal. Moreover, use is made of the fact that the filter bandwidth is always proportional to the data rate, i.e., the bandwidth and the decimation factor of the filter are in a fixed relationship with respect to one another. Correspondingly, in qualitative terms, there is more time available for calculating an output value of the filter, the lower the data rate or the bandwidth of the filter. On the other hand, it is also the case that more coefficients are required for calculating the output value given a smaller bandwidth. Meaning, in quantitative terms, that the same number of arithmetic operations per second is always required regardless of the data rate or the filter bandwidth. A suitable circuit is described below. A variant that is optimized in respect of outlay is likewise presented, for a case where the operating clock of the circuit is higher than the sampling clock at the filter input.
The circuits described below accomplish two tasks: (1) to realize low-pass filters having a bandwidth proportional to the data rate for suppressing adjacent signals; and (2) generating an output signal that is phase-synchronous with the data clock by interpolation because the sampling clock of the input signal is not synchronous with the data clock (free-running oscillator).
In order to accomplish the second task, a control loop including a phase detector, a loop filter, and a digital oscillator (xe2x80x9cDTOxe2x80x9d) is used. The oscillator is realized as an overflowing accumulator. If an overflow occurs, then a sample is interpolated from the samples of the input signal and feeds the phase detector and downstream circuits. In the steady-state condition, some of these interpolated values liexe2x80x94as desiredxe2x80x94in the center of the data pulses. The interpolated signal usually has a sampling frequency corresponding to twice the data rate (or symbol rate in the case of two-dimensional data transmission such as, e.g., QPSK or QAM). Because the two clock signals are asynchronous, the sampling instants of the signal to be interpolated generally lie between the sampling instants of the input signal. Therefore, a signal is derived from the state of the DTO after the overflow, the derived signal specifying the time interval between the desired sampling instant and the last sampling instant of the input signal. The input signal must be temporally shifted by the interval amount by the interpolation filter.
The invention accomplishes the second task by taking into account, during the interpolation of the filter coefficients from the coefficients of a prototype, not only the desired bandwidth but also the desired temporal shift. This also indicates how the invention accomplishes the first task. The bandwidth of the decimating interpolation filter must be adapted to the data rate. For example, the output signal of the loop filter can be used for such a purpose. In the steady-state condition, the output signal is proportional to the difference between the desired interpolation rate and the idle frequency of the DTO. Because the idle frequency is prescribed, it is possible to form a signal that is exactly proportional to the desired bandwidth of the filter. The loop filter has an integral element whose output signal has, in principle, the same properties, coupled with the additional advantage that the signal has significantly less noise than the output signal of the overall filter.
If, for a bandwidth fc1 of the decimating interpolation filter, M1 coefficients are required for calculating output values at the rate fa1, then M2=M1fc1/fc2 coefficients are required in the proposed method for calculating the filter coefficients for a bandwidth fc2 and an output rate fa2=fa1*fc2/fc1. It follows, therefore, that the same processing speed is required in both cases, because fa1*M1=fa2*M2. Correspondingly, it is possible, in principle, always to carry out the filter calculation with the same number of arithmetic elements, regardless of the data rate. The prototype is dimensioned for a bandwidth fc at a sampling frequency fa. In principle, the two characteristic frequencies are arbitrary, but in individual cases fc must be chosen to be low enough that, taking account of the chosen method for interpolating the coefficients, the accuracy requirements of the respective application are met. If the decimating interpolation filter is intended to have a bandwidth fc2xe2x80x94matching the sampling rate fa2 after decimationxe2x80x94and to be operated at a sampling frequency fa1, then an xe2x80x9cexpansion factorxe2x80x9d d=(fc2/fc)*(fa/fa1) results, i.e., the sampling pattern of the prototype must be xe2x80x9cexpandedxe2x80x9d by the factor d.
If the intention is to interpolate the samples of the data signal at the sampling frequency fa2, then the DTO of the control loop must be operated with the increment xcex94I=fa2/fa1 (xcex94I is supplied by the DTO, see above). As such, it is assumed that the DTO is operated at the sampling frequency fa1 and overflows at the value 1 (i.e., the output values of the DTO lie between 0 and 1). The output value I0 after the overflow can have the value xcex94I at most. It is defined that the coefficients of the prototypes are situated at points t=n where n=0, 1, etc. Correspondingly, the coefficients of the required filter that are to be interpolated are situated at the points t=xcex94t+k*d, where k=0, 1, etc., and the value xcex94t is defined by the control loop. The term k*d can be converted into k*xcex94I*(fa/fc)*(fc2/fa2)=k*xcex94I*r, where r is a constant factor (fa/fc is defined in the configuration of the prototype and problems dictate that fc2/fa2 is a constant). It likewise follows that t=xcex94t+k*d=(I0+k*xcex94I)*r, where I0+k*xcex94Ixe2x80x94disregarding noise termsxe2x80x94represent the output values of the DTO in the steady-state condition. It is thus the case that xcex94t=IO*r, in particular, holds true, i.e., the output value of the DTO after an overflow is multiplied by the constant r and is then used as a start value for the interpolation of the filter coefficients.
In accordance with another mode of the invention, the determining step is performed by prescribing or calculating first coefficients of a prototype of a further selective filter at a characteristic frequency fc for a given sampling frequency fa.
In accordance with a further mode of the invention, output values I0+k*xcex94I are produced with the digital oscillator, and using the output values I0+k*xcex94I for calculating xcex94t+k*d.
In accordance with an added mode of the invention, a sampled data signal is selectively filtered and an output value of the digital oscillator after an overflow I0, multiplied by the constant       r    =                  fa        *        fc2                    fc        *        fa2              ,
is used for a start value xcex94t for an interpolation of the second coefficients (h2(t)), where fa2 represents a sampling frequency at which the data signal is interpolated.
In accordance with an additional mode of the invention, an overflowing accumulator is used as the digital oscillator.
In accordance with yet another mode of the invention, the accumulator is fed with an increment formed by adding an output signal of the loop filter to a value (Incr0) defining an idle frequency of the digital oscillator.
In accordance with yet a further mode of the invention, an input signal is fed to arithmetic units operating in parallel, each of the arithmetic units calculating a future output value of a selective filter, and an output value of an arithmetic unit having already finished a calculation at the time of the overflow is selected in the event of an overflow of the digital oscillator.
In accordance with yet an added mode of the invention, a number N of arithmetic units operating in parallel is defined based on a number K of coefficients of the selective filter simulated respectively by the coefficient and filter calculation unit, the phase detector, the loop filter, and the digital oscillator, according to the following conditions:       N     greater than =                  K        ·        fc        ·        fa2                    fa        ·        fc2              ,
where N is an integer.
In accordance with yet an additional mode of the invention, the arithmetic units are selected with a modulo-N counter, the arithmetic units are cyclically addressed with the modulo-N counter, and the modulo-N counter is incremented with each overflow of the digital oscillator.
In accordance with again another mode of the invention, a sampled data signal is selectively filtered, an accumulator in each arithmetic unit is reset if the arithmetic unit is addressed, the arithmetic unit is loaded with an output value of the digital oscillator after the overflow, an instantaneous increment value of the digital oscillator is stored, the instantaneous increment value is accumulated for each sampling clock of the input signal, an output value of the accumulator is scaled with a value       r    =                  fa        *        fc2                    fc        *        fa2              ,
for each input clock, where fa2 represents a sampling frequency at which the data signal is interpolated.
In accordance with again a further mode of the invention, a position is defined with a scaled output value of the accumulator at which a second coefficient must be interpolated for the further selective filter from the first coefficients of the prototype.
In accordance with again an added mode of the invention, a single coefficient calculation unit is provided, the second coefficients are calculated sequentially in time with the single coefficient calculation unit, the filter output values are calculated sequentially in time in a multiplier and splitting the filter output values between N accumulators, and the respective input values are selectively stored in N further accumulators.
In accordance with a concomitant mode of the invention, the respective input values are an increment and output value of the digital oscillator.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for selective filtering, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.